1. Field of the Invention
The present invention relates to a capacitor and a method of manufacturing the same, and particularly to enhancement of capacity density, simplification of a manufacturing process and reduction of ESL (Equivalent Series Inductance).
2. Description of the Related Art
Al electrolytic capacitors and laminated ceramic capacitors are known as capacitors which are broadly used at present. The Al electrolytic capacitors have a problem that liquid leak, etc. occurs due to use of electrolytic liquid, etc. Furthermore, the laminated ceramic capacitors require a burning step, and thus it induces thermal shrinkage between an electrode and a dielectric member, etc. For example, as a technique of implementing a compact and large-capacitance capacitor is known a method of manufacturing laminated electrical parts shown in JP-A-9-45577, and a capacitor and a method of manufacturing the same disclosed in JP-T-2006-512787, for example.
JP-A-9-45577 discloses a method of manufacturing laminated electrical parts having a structure that plural internal electrodes are disposed so as to confront one another through a ceramic layer. Specifically, this method comprises a step of forming metal film on a substrate, trimming the metal film by photolithography to form a predetermined electrode pattern serving as an internal electrode, and a step of forming ceramic material serving as a functional element portion in a pore portion of the electrode pattern by a dry plating method. Furthermore, JP-T-2006-512787 discloses the following capacitor. Specifically, the capacitor comprises a first electrode that is formed in a semiconductor substrate, contains a first via and a metal layer connected to the first via and is electrically connected to a first area of the semiconductor substrate, a second electrode that is formed in the semiconductor substrate, contains a second via and a metal layer connected to the second via and is electrically connected to a second area of the semiconductor substrate, and a dielectric material having a high dielectric constant disposed between the first electrode and the second electrode.
However, the background art described above has the following problems. First, in the technique disclosed in JP-A-9-45577, the electrode is formed by etching the metal film formed on the substrate. Therefore, it is difficult to increase the aspect ratio in the z direction (thickness direction). Furthermore, in the technique disclosed in JP-T-2006-512787, it is also difficult to increase the aspect ratio in the z direction because the electrode is also formed by etching. As described above, in the electrode forming technique using etching, it is difficult to increase the aspect ratio in the z direction of the electrode portion in order to increase the area defining the capacitance.